Silicon Magpie

Yashvini Varma | ECE • RTL • VLSI • ARM

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Hiii! I’m Yashvini 👋

I’m an Electronics and Communication Engineering student interested in:

• RTL design
• VLSI
• Computer Architecture
• ARM
• Open-source hardware

Projects

ARM Datapath

Exploring and visualizing a single-cycle ARM datapath and its components.

32-Register File

A TL-Verilog implementation of an ARM-style 32-register register file.

Makerchip / RTL

Open-source hardware experiments involving RTL and computer architecture.

Currently Learning

• Computer Architecture
• RTL / TL-Verilog
• VLSI and CMOS Design
• ARM
• Python

Resume

Download my resume

Find Me

GitHub

LinkedIn